1. Field of the Invention
The present invention relates to a semiconductor device which includes MOS (Metal Oxide Semiconductor) transistors, wirings etc. and a manufacturing method thereof.
2. Description of the Background Art
Conventionally, a semiconductor device which includes MOS transistors, wirings etc. is manufactured by performing an impurity injection in a semiconductor substrate and forming an insulating film and a conductive film on a surface of the semiconductor substrate.
Information of conventional art documents which relates to the invention of the present application is described below.
Japanese Patent Application Laid-Open No. 2000-353803
Japanese Patent Application Laid-Open No. 2002-231821
K. Imai et al., xe2x80x9cCMOS device optimization for system-on-a-chip applicationsxe2x80x9d, (U.S.A.). IEDM, 2000. p. 455-458
H. Watanabe et al., xe2x80x9cNovel 0.44 xcexcm2 Ti-Salicide STI Cell Technology for high-Density NOR Flash Memories and Performance Embedded Applicationxe2x80x9d, (U.S.A.). IEDM, 1998. p. 975-976
It is general that an active layer which becomes a source/drain region of a MOS transistor is composed of an extension region and a region whose impurity concentration is higher than that of the extension region. The high impurity concentration region is formed by forming a sidewall insulating film on a side of a gate electrode after forming the extension region and performing an impurity injection with the gate electrode and the sidewall insulating film as a mask. Thus, a position where the high impurity concentration region is formed is determined by a forming width of the sidewall insulating film in a channel direction of the transistor.
Generally, with regard to a MOS transistor which is used for a memory cell in a SRAM (Static Random Access Memory) etc., the high impurity concentration region is widely formed so that it is distributed close to the gate electrode. It is performed by reason of reducing a resistance value in the source/drain region. Therefore, the forming width of the sidewall insulating film is arranged to be a small value.
In the meantime, with regard to a MOS transistor which is used for a high voltage circuit part, the high impurity concentration region is formed distant from the gate electrode as compared with a case of the MOS transistor for the memory cell. It is because, with regard to the high voltage circuit part, it is desirable that the high impurity concentration region is distant from the gate electrode to prevent a phenomenon, that is so-called GIDL (Gate Induced Drain Leakage) generation (a phenomenon that when a high voltage is applied to a gate, atoms which are stably existent in a drain region separates into holes and electrons, and thus a leakage current flows between a drain and a substrate). Therefore, the forming width of the sidewall insulating film is arranged to be a large value.
In the meantime, there is a case that both the MOS transistor for the memory cell and the MOS transistor for the high voltage circuit part are formed on one semiconductor substrate. In this case, it is general that both types of the MOS transistors are formed in the same step without adding the number of steps, and the forming widths of the sidewall insulating films are determined to be identical. In other words, the forming width of the sidewall insulating film is arranged to be a value fitting to either of the MOS transistors. Generally, in order to give priority to preventing a drain voltage breakdown in the high voltage circuit part, the forming width of the sidewall insulating film is determined to suit to the MOS transistor for the high voltage circuit part.
However, essentially as described above, it is desirable to make small the forming width of the sidewall insulating film in the MOS transistor for the memory cell and make large the forming width of the sidewall insulating film in the MOS transistor for the high voltage circuit part.
Moreover, there is a case that the active layer such as the source/drain region etc. which is formed by performing the impurity injection into the semiconductor substrate and the wiring which is formed near the active layer on the semiconductor substrate are short-circuited by a shared contact plug. In that time, as described in FIG. 23 of the patent document No. 2000-353803, there is a case that the sidewall insulating film formed on a side of the wiring is removed.
When the sidewall insulating film is removed as described above, a problem arises as described below. In other words, under the sidewall insulating film, the active layer has a low impurity concentration caused by a low injection rate of the impurity, and thus a value of a contact resistance between that part of the active layer and the shared contact plug is liable to become high. Moreover, a part of the semiconductor substrate which is under the sidewall insulating film is liable to be damaged caused by an etching when the sidewall insulating film is removed, therefore, a PN junction between the active layer and the semiconductor substrate is not definitely formed, and a junction leakage current often increases.
It is an object of the present invention to provide a semiconductor device and a manufacturing method thereof which is suited for forming both a transistor for a memory cell and a transistor for a high voltage circuit part on one semiconductor substrate, and moreover, has little deterioration of an electrical characteristic in the structure that a sidewall insulating film in a shared contact plug part is removed.
According to the first aspect of the present invention, a manufacturing method of a semiconductor device includes the following steps (a) to (f).
(a) A conductive film is formed on a semiconductor substrate.
(b) The conductive film is patterned by a photolithography technique and an etching technique.
(c) A first active layer is formed by performing an impurity injection in proximity of the patterned conductive film in a surface of the semiconductor substrate.
(d) An interlayer insulating film is formed on a surface of the semiconductor substrate.
(e) A contact hole in which both the first active layer and the conductive film are exposed is formed in the interlayer insulating film by a photolithography technique and an etching technique.
(f) A second active layer is formed by performing an impurity injection on a surface of the semiconductor substrate which is exposed in the contact hole.
The contact hole in which both the first active layer and the conductive film are exposed is formed, and the second active layer is formed on the surface of the semiconductor substrate which is exposed in the contact hole. By reason of forming the second active layer, when a conductive substance is filled in the contact hole and a shared contact plug which conducts to both the first active layer and the conductive film is formed, a contact resistance between the shared contact plug and the first active layer can be reduced than ever.
According to the second aspect of the present invention,
a semiconductor device includes a semiconductor substrate, a first transistor and a second transistor.
The first transistor includes a first gate electrode which is formed on the semiconductor substrate, a first sidewall insulating film which is formed on a side of the first gate electrode on the semiconductor substrate and first source/drain active layers which are formed in the semiconductor substrate.
The second transistor includes a second gate electrode which is formed on the semiconductor substrate, a second sidewall insulating film which is formed on a side of the second gate electrode on the semiconductor substrate and second source/drain active layers which are formed in the semiconductor substrate.
Layers of an insulating film which composes the second sidewall insulating film are more in number than layers of an insulating film which composes the first sidewall insulating film, and accordingly, a width of the second sidewall insulating film in a channel direction of the second transistor is larger than a width of the first sidewall insulating film in a channel direction of the first transistor.
By reason that the width of the second sidewall insulating film is larger than the width of the first sidewall insulating film, in the second transistor, the source/drain active layer can be formed in the position more distant from the gate electrode as compared with the first transistor. Thus, while using the second transistor for a high voltage circuit part and the first transistor for a memory cell, a semiconductor device which is suited for forming both the transistor for the memory cell and the transistor for the high voltage circuit part on one semiconductor substrate can be obtained.
These and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.